Nvidia Scraps Quad-Die Rubin Ultra GPU Design, Cites Packaging Yield Issues
- Nvidia canceled the four-die Rubin Ultra GPU design roughly three months after unveiling it at GTC 2026, reverting to a dual-die architecture [1]
- TSMC's CoWoS-L packaging suffers severe substrate warpage when arranging four near-reticle-limit dies in a 2×2 matrix with 16 HBM4E stacks, making yields uneconomical [3]
- SemiAnalysis estimates the revised dual-die Rubin Ultra delivers approximately 50% less scale and performance per package than the original design [3]
- TSMC's next-generation CoPoS (Chip-on-Panel-on-Substrate) technology could resolve the warpage issue but is not expected in volume production until late 2028 or early 2029 [3]
- NVDA shares traded at $198.24 on June 30, down 6.1% over the past month but up 25.5% year-over-year [4]
Nvidia has abandoned the quad-die configuration for its upcoming Rubin Ultra data center GPU, scrapping an ambitious four-chiplet design that proved too difficult to manufacture with current advanced packaging technology. The decision, first reported by semiconductor research firm SemiAnalysis and corroborated by TrendForce citing Commercial Times, marks one of the most significant product architecture retreats in Nvidia's recent history [1][2].
The original Rubin Ultra, unveiled at GTC 2026 in March, was designed to pair four compute dies fabricated on TSMC's N3P process with 16 HBM4E memory stacks in a single package using TSMC's CoWoS-L (Chip-on-Wafer-on-Substrate with local silicon interconnect) advanced packaging. However, the 2×2 die matrix created severe substrate warpage — the physical bowing of the package substrate under thermal and mechanical stress — causing dies to lose contact and fail signal transmission [3].
The replacement design reverts to two compute dies per package, a configuration consistent with the standard Rubin GPU already slated for H2 2026 production. SemiAnalysis estimates the revised Rubin Ultra will deliver roughly half the compute scale and performance of the original quad-die design at the package level, though Nvidia may attempt to recover system-level performance through a 2+2 board-level arrangement that pairs two dual-die packages on a single board [1][3].
The Packaging Bottleneck
The root cause is a fundamental limitation of TSMC's CoWoS-L advanced packaging platform. A four-die configuration would have expanded the package size to approximately 7.5–8 times the reticle limit, the maximum area a lithography system can pattern in a single exposure. At that scale, yield rates collapse and per-unit costs become prohibitive [2].
The specific failure mode — substrate warpage — occurs when the thermal expansion coefficients of silicon dies, HBM stacks, and the organic substrate interact under reflow soldering temperatures. With four large compute dies and 16 HBM4E modules generating uneven stress across an oversized substrate, the package physically bows, breaking micro-bump connections between the dies and the interposer [3].
TSMC has a next-generation solution in development: CoPoS (Chip-on-Panel-on-Substrate), which replaces the organic substrate with a panel-level interconnect that can better accommodate large multi-die layouts. However, CoPoS pilot production is targeted for 2026, with volume production not expected until late 2028 or early 2029 — well past the Rubin Ultra's 2027 launch window [3].
Performance and Rack-Scale Implications
The original Rubin Ultra was positioned as a generational leap, doubling compute density versus the standard dual-die Rubin GPU. With the retreat to a dual-die package, the per-accelerator advantage over standard Rubin narrows significantly. Nvidia's Vera Rubin NVL72 rack system — combining 72 Rubin GPUs with 36 Vera CPUs connected via sixth-generation NVLink at 3.6 TB/s per GPU — was designed for the standard Rubin and remains on track for H2 2026 availability [5].
Reports suggest Nvidia may pursue a 2+2 board-level design for Rubin Ultra, placing two dual-die packages on a single board to approximate the original four-die compute density. This approach trades packaging complexity for board-level integration, avoiding the CoWoS-L warpage issue but potentially introducing its own thermal and power delivery challenges [1].
Competitive Context
The design retreat comes at a moment when Nvidia's dominance in AI accelerators faces growing pressure from custom silicon programs at major cloud providers. Amazon's Trainium chips, Google's TPUs, and AMD's Instinct accelerators have all gained traction in large-scale AI training and inference workloads [3].
SemiAnalysis noted that the 'CUDA ecosystem moat' — Nvidia's software stack advantage — is 'showing signs of weakening,' citing deployments of significant inference workloads on Amazon Trainium and AI model training on Google TPUs. The firm warned that continued manufacturing execution issues 'will only cause more market share to be lost' [3].
Nvidia has not publicly commented on the design change. The company's shares traded at $198.24 on June 30, up 1.7% on the day but down 6.1% over the trailing month. The stock remains up 25.5% year-over-year, supported by strong Blackwell-generation demand, with a market capitalization of approximately $4.8 trillion [4].
What's Next
The standard Rubin GPU remains on schedule, with Nvidia's partners — including AWS, Google Cloud, Microsoft Azure, Oracle Cloud, and CoreWeave — planning deployments in the second half of 2026 [5]. The Rubin Ultra, now in its revised dual-die form, is still targeted for 2027, though the architecture change could shift the timeline.
For data center operators planning next-generation AI infrastructure purchases, the key question is whether the dual-die Rubin Ultra plus board-level integration can deliver the performance uplift that Nvidia originally promised. If not, the rack-scale NVLink fabric and software ecosystem will need to compensate — or operators may increasingly evaluate alternatives from AMD, Amazon, and Google for their most demanding workloads.
Companies mentioned
NVIDIA Corporation stands as a prominent provider of advanced graphics, computational, and networking solutions, operating across the United States, Taiwan, China, and numerous international markets. Its Graphics divisi…
Advanced Micro Devices, Inc. (AMD), established in 1969 and headquartered in Santa Clara, California, operates as a global leader in the semiconductor industry. The company organizes its extensive operations into two pr…
Taiwan Semiconductor Manufacturing Company Limited (TSMC), along with its affiliated entities, operates globally in the semiconductor industry, specializing in the manufacturing, packaging, meticulous testing, and world…
Amazon.com, Inc. operates a vast global retail enterprise, distributing consumer goods and subscription services through both its extensive online platforms and a network of physical stores across North America and inte…
Alphabet Inc. provides a diverse range of products and digital platforms to consumers across multiple global regions, including North and South America, Europe, the Middle East, Africa, and the Asia-Pacific. The company…